`include "define.svh"

module wb_wrap(
    input wire                              clk,
    input wire                              rstn,
    input wire                              ctrl_stall,
    input wire [`PC_WIDTH - 1 : 0]          debug_pc_i,
    
    input wire [`REG_ADDR_WIDTH - 1 : 0]    wregaddr_i,
    input wire                              wregenable_i, 
    input wire [`REG_WIDTH - 1 : 0]         wregdata_i,
    output reg [`REG_ADDR_WIDTH - 1 : 0]    wregaddr_o,
    output reg                              wregenable_o,
    output reg [`REG_WIDTH - 1 : 0]         wregdata_o,
    
    output reg [`PC_WIDTH - 1 : 0]          debug_wb_pc,
    output reg [3 : 0]                      debug_wb_rf_wen,
    output reg [`REG_ADDR_WIDTH - 1 : 0]    debug_wb_rf_wnum,
    output reg [`REG_WIDTH - 1 : 0]         debug_wb_rf_wdata
);
    
    always_ff @(posedge clk) begin
        if (rstn == `reset) begin
            debug_wb_pc <= `NOP_PC;
            debug_wb_rf_wen <= 4'b0000;
            debug_wb_rf_wnum <= 5'b00000;
            debug_wb_rf_wdata <= `ZERO_REG;
        end else if (ctrl_stall) begin
            debug_wb_pc <= debug_wb_pc;
            debug_wb_rf_wen <= 4'b0000;
            debug_wb_rf_wnum <= debug_wb_rf_wnum;
            debug_wb_rf_wdata <= debug_wb_rf_wdata;
        end else begin
            debug_wb_pc <= debug_pc_i;
            debug_wb_rf_wen <= {4{wregenable_i}};
            debug_wb_rf_wnum <= wregaddr_i;
            debug_wb_rf_wdata <= wregdata_i;
        end
    end
    
    always_comb begin
        wregdata_o = wregdata_i;
        wregenable_o = wregenable_i;
        wregaddr_o = wregaddr_i;
    end
    
endmodule
